As integrated circuit (IC) geometries continue to shrink, susceptibility to electrostatic discharge (ESD) damage increases. In particular, decreasing gate oxide thicknesses in MOS (metal-oxide-semiconductor) devices relative to breakdown voltage has resulted in an increased susceptibility to damage from the application of excessive voltages. During an ESD event, charge is transferred between one or more pins of the integrated circuit and another conducting object. This charge transfer can develop voltages that are large enough to break down insulating gate oxides, leading to failures, such as contact spiking, silicon melting, or metal interconnect melting.
Many attempts have been made in the prior art to protect semiconductor devices from such ESD events. One common approach uses protection circuits connected to I/O (input-output) pads of an IC to safely dissipate the energy associated with ESD events without causing any damage to the internal circuitry.
An exemplary embodiment of an ESD protection circuit is shown in the FIG. 1. Referring to FIG. 1, the ESD protection circuit 100 includes a protected ESD bus or node 102 that is connected to one or more input pads 104 through a number of diodes D1I, D2. The ESD protection circuit 100 is configured to couple the protected VESD node 102 to a negative power supply, VSS, through a FET (field effect transistor) triggered SCR (silicon controlled rectifier) circuit 106. In circuit shown in FIG. 1, the SCR 106 includes a NPN bipolar transistor Q1 and a PNP bipolar transistor Q2 interconnected so that each transistor receives base current from the collector terminal of the other, and a FET 108 configured to trigger the SCR into conduction, thereby providing a low-impedance path to safely shunt an ESD charge to VSS. The ESD protection circuit 100 further includes a number of resistors R1, R2 and R3, to insure proper operation of the SCR 106 and FET 108, to provide predetermined impedance when the circuit is conducting and/or to limit current through the FET during an ESD event. In a normal operating state the ESD protection circuit 100 is in a high-impedance “OFF” state, thereby reducing externally-sourced leakage currents into pads 104. In an “ON” state the ESD protection circuit 100 is configured to transfer charge from the VESD bus to VSS when a voltage on the VESD node 102 reaches a predetermined threshold or trigger voltage.
A cross-sectional view of the ESD protection circuit of FIG. 1 is shown in FIG. 2. Generally, the circuit is fabricated on a P-type silicon substrate 200, and includes a first P+ ohmic contact 202, a N+ drain region 204, a N+ source region 206, a channel region 208 between the spaced apart drain and source regions, a N-well region 210, a second N+ ohmic contact 212, a third N+ ohmic contact 214, and a P+ junction region 216 formed in the N-well. A layer of dielectric material overlies a portion of substrate, including a gate dielectric region overlying the channel region. A conductive silicide layer 218 is formed over several of the diffusion regions, and a transistor control gate 220 is formed over the dielectric overlying the channel region. Structures labeled FOX are field oxide regions.
Several trigger mechanisms have been used in the past to turn on SCR protection devices for ESD. These trigger mechanisms include avalanche breakdown of a drain diode of a MOS transistor, MOS transistor source-drain current and collector current from bipolar transistor. For example, in the circuit described above when the voltage on ESD bus reaches the NMOS drain breakdown voltage, current begins to flow in the N-well 210 between N+ regions 212 and 214 as the drain junction 204 breaks down, and injects holes into the substrate. The hole injection into substrate forward biases the N+ source 206 injecting electrons, which are collected by both the N+ drain 204, and the adjacent N-well. Simultaneous with the drain breakdown, the current flowing between the N+ regions 212 and 214 results in a voltage drop across the N-well, which causes the P+ region 216 to become forward biased resulting in an injection of holes into substrate, thereby hastening the transition of the SCR into a latched state.
The above described protection circuit works well with current generation of devices having circuit geometries much greater than 65 nm (nanometers). However, it will be appreciated that although the well current immediately starts flowing as soon as the FET drain junction starts avalanching, the SCR does not trigger until the FET reaches drain breakdown voltage. Thus, the turn on characteristic of the protection circuit is too slow for devices using technologies less than 65 nm, and in particular for fast ESD events, such as those described by the Charged Device Model (CDM) failures.
In addition, conventional protection circuits such as in FIG. 1 have a trigger voltage that can be high enough to cause damage in thin gate dielectrics that need to be protected.
Accordingly, there is a need for a fast triggering ESD protection circuitry for protection in technologies less than 65 nm, and in particular for fast ESD events, such as those described by the CDM. There is also a need for an ESD protection circuitry in which trigger current and voltage can be set independently using many circuit and/or layout parameters, and where the trigger voltage is low enough.
The present invention provides a solution to these and other problems, and offers further advantages over conventional ESD protection approaches.